Many memory devices such as mass storage memory devices may include a large number of memory cells, one or more of which may be initially defective due to non-ideal manufacturing processes, or may become defective during application due to degradation and wear out. The initial defective memory cells or blocks may be identified by the manufacturer and provided through the data sheet of the memory device. Many systems may keep track of bad memory cells or blocks during the life of the memory device and store a list of defective one or more faulty addresses associated with one or more bad memory cells or blocks.
Memory devices may include embedded built-in-self-test (BIST) engines that can facilitate testing of each memory device. In addition, test/scan logic may be used to test memory interfaces. The test/Scan logic may include a sampling stage between the data-in (DIN) and data-out (DOUT) ports of the memory device. The sampling stage may add observability of the memory interface during scan/test modes by entering the memory into a bypass mode, during which the memory is not accessible.